Field of Invention
The present invention relates to a field of semiconductor chip package, and more particularly, to a manufacturing method of chip package structure having a coating layer.
Description of Related Art
The chip package structure can be classified into two categories such as a solderless terminal type and a solder terminal type, in which the solderless terminal type belongs to a land grid array (LGA) packaging technology, and the solder terminal belongs to a ball grid array (BGA) packaging technology. It is known that electromagnetic interference (EMI) shielding technology or high-temperature coating technology are widely used in the chip package structure of the solderless terminal type. The electromagnetic interference (EMI) shielding layer is often formed by physical vapor deposition (PVD) process, such as sputtering. For example, the forming process of the electromagnetic interference (EMI) shielding layer is performed under a high-vacuum environment, and the process temperature approximately approaches 300 degrees Celsius. However, the EMI technology or the high-temperature coating technology cannot be adopted in a forming process of a chip package structure of the solder terminal type. To be specific, when a high-temperature coating process is performed on the chip package structure of the solder terminal type, the process temperature may be greater than a melting point of soldering terminals (e.g., the melting point of tin solder balls is about 217 degrees Celsius). Consequently, a high-temperature coating layer cannot be successfully formed on a top surface and side surfaces of the chip package structure of the solder terminal type.
Furthermore, in the conventional manufacturing processes of the chip package structure, an encapsulant covers a plurality of elements in large areas, and then the elements are diced or singulated to separate from one another. As known, the high-temperature coating process is usually performed before the dicing or singulation step. Meaning, the coating layer is exclusively formed on the top surface of the chip package structure, which indicates that there is no expected protection for the side surfaces of the chip package structure. It should be noted that if the high-temperature coating process is simply performed after the dicing or singulation step, there is a problem of a greatly increase in the manufacturing cost. Also, a deterioration of product yield may arise since the encapsulant further contaminates a back surface of the chip package structure and soldering terminals located on the back surface.